A METHODOLOGY FOR THE CONSTRUCTION OF ACCURATE TIMING MACROMODELS FOR DIGITAL CIRCUITS

Ayman I. KAYSSI

The development of a general macromodeling strategy for delay computation based on dimensional analysis is the most important contribution of this work. We have demonstrated the power of dimensional analysis as an indispensable tool in delay macromodeling, and shown how to apply it in a systematic way for general behavioral macromodeling applications. When dimensional analysis is used in conjunction with circuit simulation and the Monte Carlo method, the resulting macromodels provide excellent accuracy without compromising efficiency.

The second general contribution is context delay modeling and the inclusion of transition time effects in timing analysis. The long path delays obtained for a front‑end 2‑context gate delay model were within a few percent of circuit simulation, indicating the accuracy of both the context modeling approach and the gate macromodels.

We have developed the first GaAs DCFL macromodel that takes into account the effects of input rise/fall times, nonlinear Schottky diode current, and input proximity. The accuracy and simplicity of the GaAs DCFL macromodels stem directly from the application of dimensional analysis. We have also derived CMOS macromodels by first calculating a general voltage waveform at output of a CMOS inverter, and then by using dimensional analysis, which allowed us to extend the inverter macromodel to general CMOS static gates. The CMOS inverter macromodel is one‑dimensional for purely capacitive loads. For RC loads, which model the loading of RC interconnect on the driving inverter, the macromodel is two‑dimensional.

A general timing macromodel for RC interconnections was developed. It takes into account the threshold levels at which the delay is measured, and the input rise/fall times. The macromodel was obtained after approximating the transfer function by a one‑zero, two‑pole function. The accuracy of the interconnect was demonstrated, indicating the validity of the assumptions that we made.

Off‑chip lossy and lossless point‑to‑point interconnections were macromodeled using dimensional analysis. The approach yielded a very simple linear model for lossless lines, and a quadratic model for lossy lines. The lossy line macromodel was used to study the sensitivity of line delay to various circuit parameters.

Finally, we have shown that failure to account for signal transition times in path delay computations can cause significant errors. We proposed two solutions: The first is an extension to the standard fixed‑delay CPM algorithm. The second consists of context‑based delay modeling step followed by standard fixed‑delay CPM techniques. Both approaches have been shown to predict path delays with a high degree of accuracy.

The use of delay macromodels in timing analysis can be extended to circuit optimization. Since the macromodel takes into account the sizes of the transistors, the capacitive loading and the gate fanout, the optimization application can rely on the macromodel to provide accurate results during optimization. Macromodels for power dissipation and switching noise can also be derived and incorporated in the optimization process.

For interconnect macromodeling, the inductive effects were neglected for on‑chip interconnections. An extension of the RC macromodel would be the inclusion of the effects of inductance. For true system‑wide timing analysis, a general macromodel for off‑chip interconnect, similar to the one we derived for on‑chip interconnect is needed. Off‑chip interconnect, however, may not be modeled accurately except by coupled transmission lines, which present certain difficulties for accurate delay modeling. Further research in this area is needed for system‑wide timing analysis and optimization.